The present invention relates to a method of forming lead-free solder bump interconnections on semiconductor wafers for flip-chip bonding applications.
With flip-chip interconnect technology, a raised electrically conductive contact called a xe2x80x9cbumpxe2x80x9d is first formed onto the input/output connection pads of an integrated circuit (IC) which is subsequently assembled face-down (or xe2x80x9cflip-chipxe2x80x9d bonded) without the use of conventional wire bonds or leads. Various bump interconnection media have been proposed including gold, lead-tin solder, nickel, copper, and conductive polymers. Lead-tin bumps are particularly attractive due to the self-alignment and self-planarizing properties (upon reflow) of solder which allows for a more robust and manufacturable attachment process. In addition to providing electrical contact, the solder bump also forms a mechanical, and thermal connection between the chip and substrate. The use of lead-tin solder bumps for flip-chip applications was first introduced by IBM in the 1960""s in their C4 (controlled-collapse-chip-connection) technology using a method of evaporation for fabrication of the bumps.
Primary advantages of flip-chip technology as compared to other interconnection techniques include:
i) the capacity to significantly increase the total number of connections that can be made to the chip because the small bump contacts can be placed virtually anywhere on the surface of the chip and at points convenient for a particular application (unlike xe2x80x9cperimeter-onlyxe2x80x9d bonding technologies such as wire-bonding and tape-automated-bonding (TAB));
ii) the potential to shrink the die size and obviate the need for long metallization lines leading to the periphery pads which would favourably impact both the IC manufacturing yield and reliability;
iii) lower electrical resistance and inductance values leading to faster interconnection speeds and lower power consumption;
iv) better thermal dissipation performance due to conduction through the solder bumps and exposed rear surface of the IC after flip-chip bonding;
v) provision for a smaller, lighter, and more compact package with overall lower packaging cost per pin.
The selection of the precise composition of a solder bump material is conventionally influenced by a variety of factors, most particularly melting point. Attention must be paid to the solder melting point, particularly where the chip is bonded to a substrate which are mostly formed of low-cost organic materials with relatively low Tg (glass transition temperatures). When the IC is flip-chip bonded, it is normally heated to a temperature which is typically 20-30xc2x0 C. higher than the melting point of the solder. Too high a melting point for the solder bump may therefore lead to damage of the substrate.
The two most common bump materials currently in use for flip-chip bonding applications consist of pure gold and lead-tin based alloys. The former are used mainly to flip-chip a silicon IC onto liquid crystal displays (LCDs) or in TAB packages. Lead-tin solder bumps are used primarily for flip-chip-on-board or flip-chip-in-package applications. Solder bumps are typically preferred over gold bumps due to their lower cost and self-planarizing and self-aligning reflow characteristics which provides for a more manufacturable and robust flip-chip bonding process.
Lead-tin alloys commonly employed as solder bumps include in particular 95 wt %Pb/5 wt %Sn, 97 wt %Pb/3 wt %Sn, and eutectic 37 wt %Pb/63 wt %Sn. Lead-based solders with additions of In, Ag, and Bi have also been proposed.
With growing environmental awareness, a worldwide ban on the use of lead-containing solders in electronic products is under consideration since the lead from such products, which are typically disposed of in landfills, eventually leaches into the drinking water system. Laws restricting the use of lead in electronics products may be enacted in the European Community, and similar legislation to ban lead is pending in the United States and in Japan. Efforts to identify suitable lead-free finishes for electronic components has thus far been focused mainly on printed circuit boards, lead frame packages, and in the selection of solder pastes. Little attention has been paid to the fabrication of bump interconnections for flip-chip applications.
Lead-free solders have been proposed including those based on indium and its alloys with bismuth, tin, antimony, zinc and silver.
What is required are lead-free solder bump compositions which can be directly substituted for the lead-tin alloys conventionally used for flip-chip applications, and a fabrication method employing such a lead-free solder bump composition.
It is proposed in U.S. Pat. No. 5,410,184 assigned to Motorola to utilise a lead-free solder alloy having tin as a predominant component, between 2-8%wt or more preferably 3xe2x80x945%wt copper and up to 1.5%wt silver. This solder requires the presence of an amount of copper at preferably 3-5%wt so as to retain formation of a certain degree of intermetallics for bond integrity. It is found however that this composition may suffer problems of bond embrittlement owing to an excessive formation of the tin-copper intermetallics.
The present invention seeks to provide a process for forming solder bumps which overcomes the problems mentioned above.
According to a first aspect the invention resides in a method of forming solder bumps on a chip or wafer for flip-chip applications, comprising the steps of providing a chip or wafer having a plurality of metal bonds pads which provide electrical connection to the chip or wafer, and applying a solder bump comprising pure tin or a tin alloy selected from tin-copper, tin-silver, tin-bismuth or tin-silver-copper by an electroplating technique, and melting the solder bumps by heating to a temperature above the bump melting point to effect reflow.
The solder is more preferably one of pure tin, tin-copper alloy of less than 2% weight copper or more preferably about 0.7% by weight copper, tin-silver alloy having less than 20% by weight silver or more preferably about 3.5% by weight silver, or 10% by weight silver, tin-bismuth having between 5% and 25% by weight bismuth or more preferably about 20% by weight bismuth, or tin-silver-copper alloy having less than 5 wt % silver, and preferably about 3.5 wt %Ag, less than 2 wt % copper and preferably about 0.7 wt %Cu, with the balance being tin.
It is found that pure tin or the tin alloys can be directly substituted for the conventional lead-tin alloys, whilst the solder bumps can be formed using electroplating to give particularly well-defined, regular bumps. The tin-based solders identified are also compatible with existing reflow processes and materials, and with surface mount techniques and equipment.
In the case of the binary alloys tin-copper, tin-silver and tin-bismuth the elements can be simultaneously co-deposited as the alloy from a single plating solution.
In an alternative technique the elements can be sequentially deposited from separate plating solutions, which form the requisite alloys on heating during the reflow process. This sequential plating is particularly applicable also to the ternary alloy tin-silver-copper. In this case the alloy is deposited by depositing one or other of tin-copper alloy from a single plating solution by co-deposition, or elemental silver, followed by deposition of the other, the ternary alloy forming on heating. It is also possible to sequentially deposit each of the three elements.
The chip or wafer may be, before electroplating, provided with a sputtered layer or layers of metal which function as a diffusion barrier, barrier to oxidation, adhesion, and plating contact layer (electrical buss). A layer of thick photosensitive polymer material such as photoresist (negative or positive tone) or dry film with a thickness of between 25-200 xcexcm is used to define the location and volume of the solder bumps to be plated. The provision of thick photoresist or dry-film is important to ensure sufficient height and volume of the plated solder bump without causing shorting to the next adjacent bump, and to maintain the necessary stand-off height between the chip and the substrate in order to compensate for differences in thermal coefficients of expansion of the chip and the substrate as well to provide a sufficient gap for underfill material to flow between the chip and the substrate after flip-chip bonding.
The electroplating of the solder bumps can be carried out using either direct current (DC) or pulsed alternating current. The current and voltage values depend on the size of the wafer and the total exposed surface area to be plated. Preferable DC plating parameters range between 3-5 V with a current of between 0.05-0.1 A. In a preferable pulsed plating cycle voltage alternates between +5 V for about 1 millisecond, a zero voltage portion for about 1 millisecond or less, between xe2x88x925 to xe2x88x9210 V for 1 millisecond, followed by zero voltage for about 1 millisecond.
Either rack or fountain plating equipment may be used for plating of the solder on the wafers.
According to a further aspect the invention resides in a method for forming solder bumps on a chip or wafer for flip-chip applications comprising the steps of: (a) providing a chip or wafer having a passivation layer and a plurality of exposed metallic bond pads; (b) applying at least one solder-wettable metal layer to the bond pad; (c) applying a photosensitive layer to the chip or wafer having openings at the portions of the bond pads; (d) applying a solder comprising pure tin, or a tin alloy selected from tin-copper, tin-silver, tin-bismuth, or tin-silver-copper by an electroplating technique; (e) removing the photoresist layer; and (f) melting the solder bumps to effect reflow.
The invention also resides in a chip or wafer when formed according to the methods described above.